Huawei bets on a new law of physics to outmaneuver chip restrictions

The Tau Scaling Law and LogicFolding architecture mark China's most ambitious attempt yet to redefine semiconductor progress on its own terms.

Moore's Law has governed the semiconductor industry's ambitions for more than five decades. Huawei thinks it has a replacement.

At the 2026 IEEE International Symposium on Circuits and Systems in Shanghai on May 25, 2026, He Tingbo, chair of Huawei's Scientist Committee and president of its semiconductor business, presented the Tau (τ) Scaling Law, a new principle that proposes shifting the industry's guiding metric from geometric transistor miniaturization to time scaling.

Rather than making transistors smaller, the framework focuses on compressing the time it takes signals and data to travel through chips and computing systems. He's peers have already taken to calling it "Her's Law."

For context, US export restrictions have effectively cut China off from the advanced lithography equipment needed to manufacture chips at the frontier nodes that TSMC and Samsung currently occupy. The Tau Scaling Law, backed by a new chip architecture called LogicFolding, is Huawei's response to that constraint.

According to Huawei's official statement, the framework operates across four levels simultaneously. At the device level, it minimizes resistance and parasitic capacitance in transistors and interconnects. At the circuit level, LogicFolding breaks the physical boundaries of traditional circuit layouts, shortening critical-path wiring to reduce resistive and capacitive load.

At the chip level, full-stack coordinated design of software, architecture and silicon drives workload efficiency. At the system level, a new interconnect protocol called UnifiedBus delivers unified memory addressing for SuperPoDs, cutting communications latency across large-scale AI deployments.

The claim attached to all of this is significant: Huawei expects its high-end chips, designed under the Tau Scaling Law, to reach transistor density equivalent to 1.4nm processes by 2031. The company frames this as density equivalence rather than lithographic parity, a distinction that matters technically, and one the industry will be stress-testing for years.

He said Huawei has spent six years quietly building towards this moment, designing and mass-producing 381 chips based on the Tau Scaling Law across smartphones, AI computing and other sectors. "I used to think it may take us 10 years, but six years we are here," she told the ISCAS audience. The company's new Kirin chips, due in Fall 2026, will be the first commercial products to carry the LogicFolding architecture. "Before winter 2026, we will bring the surprise… a big leap ahead," He added.

The announcement also carries implications for Huawei's AI chip roadmap. The Ascend series, already central to powering Chinese AI models including DeepSeek's V4, is on a structured release schedule, with the Ascend 950 series due this year, the Ascend 960 in 2027 and the Ascend 970 in 2028.

SMIC shares rose 7.6% on Monday following the news, a market signal that investors are reading this as industrial progress rather than forward-looking positioning. He closed with a message that framed the Tau Scaling Law as an open invitation rather than a proprietary claim.

"No single company can independently find all the answers along the path of semiconductor evolution," she said, per Huawei's official statement. "We look forward to working closely with scientists, engineers, and industry partners around the world."

What Huawei has put on the table is six years of constrained R&D that produced 381 mass-produced chips and a principle coherent enough to present at an IEEE symposium. The density equivalence claim for 2031 is still to be proven, but the groundwork, at least, is no longer theoretical.