Huawei's Kirin 9050 Pro brings vertical stacking into production silicon

The chip is the first to ship with LogicFolding, the architecture Huawei is counting on to keep improving performance without leading-edge lithography.

Huawei launched the Kirin 9050 Pro on Monday, the first commercial chip built on the LogicFolding architecture the company introduced in research papers four months ago. It is also the first new high-performance Kirin unveiled at a Huawei flagship product event in six years, according to local Chinese reports.

The chip debuted in the Mate XT 2, a tri-fold handset starting at 19,999 yuan (US$2,980). Richard Yu Chengdong, chairman of Huawei's consumer business group, called it the company's "most powerful Kirin chip ever" and said overall device performance improved 42% over the previous-generation Mate XTs.

Huawei said at the launch that the Kirin 9050 Pro raised transistor density from 155 million transistors per square millimetre to 238 MTr/mm² without conventional geometric scaling, meaning without smaller process nodes or the lithography equipment needed to print them, TechNode reported. Performance cores peak at 3.1GHz, peak single-core performance is up 24% and multi-core performance up 52% against the previous generation. The area taken up by the chip's high-speed on-chip network data paths fell by 55%.

What LogicFolding does

Conventional 3D integration stacks largely self-contained dies on top of one another, with each layer operating as its own unit. LogicFolding splits core computing functions across two active layers designed to work together as one. Adding vertical interconnects inside the chip shortens the distance signals travel, which reduces both delay and the energy lost moving data between the processing blocks that dominate a mobile chip's power budget.

The approach sits under what Huawei calls its Tau Scaling Law, set out in a May paper by He Tingbo, chairwoman of the company's Scientist Committee and president of its semiconductor business department. That paper argued the method could reach transistor densities equivalent to a 1.4-nanometre process by 2031 without extreme ultraviolet lithography machines, which remain blocked for sale to China under US-led export controls.

Stacking active logic vertically concentrates power in a smaller volume, and analysts had questioned for months whether the design could shed the heat. Huawei published a third paper on ChinaXiv on Friday reporting that the chip ran cooler than its predecessor while packing 55% more transistors per square millimetre and cutting power consumption by up to 66% on some tasks. The paper has not been peer reviewed. Its density figure also runs slightly ahead of the 53.5% implied by the numbers Huawei gave at Monday's launch.

The manufacturing bill

Bonding two active silicon layers is harder than stacking finished dies. It requires precise wafer thinning and microscopic vertical wiring, steps that can weigh on factory yields, according to Leslie Wu, chief executive of semiconductor consultancy RHCC, in a research note. LogicFolding is "first and foremost a compensatory route", said Leslie Wu, chief executive of semiconductor consultancy RHCC, in a research note. Wu said the choice was born of external constraints, and that the economics look less compelling for companies that can simply print smaller transistors on a single layer.

Venkat Somala, a researcher at Epoch AI, wrote on Friday that smartphone processors offered a far gentler starting point than AI accelerators. Smaller dies make production losses easier to absorb, lower power draw reduces the thermal problem, and high handset volumes give assembly lines the repetition they need to mature.

Scaling the same technique to Huawei's Ascend line would be considerably harder given the larger die sizes and heat output involved, Somala said, adding that mastering it would be "key to Huawei's competitiveness beyond 2030". Huawei has said it expects to rely on established 3D stacking for the rest of the decade before bringing LogicFolding to its flagship Ascend 990 around 2030.

Every performance figure attached to the Kirin 9050 Pro so far comes from Huawei's own measurements, and no independent teardown has been published to confirm that two genuinely active layers are present or how the density gain was achieved.

The spending behind the effort is visible in Huawei's half-year results. Research and development rose 25% year-on-year to 121.4 billion yuan (US$18 billion) while net profit fell 36% to 23.8 billion yuan. Revenue grew 9.6% to 467.8 billion yuan.