Siemens and TSMC add AI agent to automate chip design rule fixes

The agent, enabled across digital and custom chip design flows, is part of an expanded collaboration that also covers A14 certification and advanced packaging support.

Siemens has expanded its collaboration with TSMC on AI-powered chip design, enabling an AI agent that automatically fixes design rule check (DRC) errors across digital and custom integrated circuit (IC) design flows.

DRC is the stage where a chip layout is checked against the foundry's manufacturing rules before it goes into production. The agent runs on Siemens' Calibre software and is integrated with its Aprisa and Solido tools. Siemens said it was designed to help engineering teams reduce manual effort and shorten time to tapeout, the point at which a design is finalised and sent for manufacturing.

The company did not disclose figures on time saved or say when the agent would be generally available.

Siemens announced the work at TSMC's 2026 North America Open Innovation Platform (OIP) Ecosystem Forum in Santa Clara, California, on September 23. Synopsys and Cadence also announced A14 certifications and agentic AI design work with TSMC at the event.

AI agents and A14 certification

Siemens said it is also working with TSMC on its Fuse EDA AI System and Fuse EDA AI Agent, which are designed to run long, multi-step design tasks across several EDA tools and check their own results. The company said the Fuse agent uses Nvidia AI technologies to improve token efficiency in long-running engineering workloads.

On process technology, four of Siemens' Calibre verification tools, Calibre nmDRC, nmLVS,

xACT and PERC, are now certified for TSMC's A14 process. Certification for Aprisa and mPower analog software on A14 is underway.

Ankur Gupta, executive vice president of EDA IC software at Siemens Digital Industries Software, said the collaboration combined Siemens' design software with TSMC's process and packaging technologies.

"By combining Siemens' EDA portfolio with TSMC's leading process and packaging technologies, we are helping customers achieve new levels of productivity, speed and design confidence," he said.

Aveek Sarkar, director of the ecosystem and alliance management division at TSMC, said the foundry's work with partners such as Siemens was focused on automation that engineers could trust as designs became more complex.

"Our collaboration with OIP partners like Siemens focuses on delivering intelligent, trusted automation that empowers engineers to navigate rising design complexity while achieving stringent performance and energy-efficiency targets," he said.

Packaging support still in progress

Siemens said it has enabled multi-machine support in Calibre 3DStack Advanced for verifying connections between stacked chiplets on TSMC-SoIC, the foundry's wafer-level 3D chip stacking platform. Certification work for CoWoS-L, a version of TSMC's advanced packaging used for large AI chips, is underway.

The company's Calibre 3DThermal software has been certified for thermal analysis on TSMC's A16 process and 3DFabric packaging technologies. A thermal reference flow for TSMC-COUPE, the foundry's co-packaged optics platform, is still in progress.

Siemens has also opened its Xcelerator Academy, an on-demand training programme for its EDA software, to TSMC's Design Center Alliance partners. Previously it was available to mutual customers only. The programme includes a digital implementation flow tutorial based on TSMC's 5nm process.